Issued Patents 2020
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10784864 | Low power integrated clock gating system and method | Matthew Berzins, Lalitkumar Motagi | 2020-09-22 |
| 10748932 | Method for high performance standard cell design techniques in FinFET based library using local layout effects (LLE) | Abhishek Ghosh, Parvinder Kumar Rana | 2020-08-18 |
| 10715118 | Flip-flop with single pre-charge node | Sandeep B V, Shreyas Samraksh Jayaprakash, Abhishek Ghosh, Parvinder Kumar Rana | 2020-07-14 |