| 10854522 |
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas |
Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more |
2020-12-01 |
| 10803221 |
Snap-to valid pattern system and method |
Elizabeth Lagnese |
2020-10-13 |
| 10777472 |
IC with test structures embedded within a contiguous standard cell area |
Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more |
2020-09-15 |
| 10622344 |
IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a substantially uniform variant of the original set of design rules and methods for making the same |
Elizabeth Lagnese |
2020-04-14 |
| 10593604 |
Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells |
Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more |
2020-03-17 |