| 10871967 |
Register read/write ordering |
Aaron L. Smith |
2020-12-22 |
| 10860924 |
Hardware node having a mixed-signal matrix vector unit |
— |
2020-12-08 |
| 10819657 |
Allocating acceleration component functionality for supporting services |
Andrew R. Putnam, Stephen F. Heil, Michael David Haselman, Sitaram V. Lanka, Yi Xiao |
2020-10-27 |
| 10776115 |
Debug support for block-based processor |
Aaron L. Smith |
2020-09-15 |
| 10768936 |
Block-based processor including topology and control registers to indicate resource sharing and size of logical processor |
Aaron L. Smith |
2020-09-08 |
| 10719321 |
Prefetching instruction blocks |
— |
2020-07-21 |
| 10705892 |
Automatically generating conversational services from a computing application |
Oriana Riva, Jason Alan Kace, Jiajun Li |
2020-07-07 |
| 10691413 |
Block floating point computations using reduced bit-width vectors |
Daniel Lo, Eric S. Chung |
2020-06-23 |
| 10678544 |
Initiating instruction block execution using a register access instruction |
Aaron L. Smith |
2020-06-09 |
| 10606672 |
Micro-service framework derived from third-party apps |
Oriana Riva, Suman Kumar Nath, Yongjian Hu |
2020-03-31 |
| 10606651 |
Free form expression accelerator with thread length-based thread assignment to clustered soft processor cores that share a functional circuit |
Stephen F. Heil, Sitaram V. Lanka, Andrew R. Putnam, Aaron L. Smith |
2020-03-31 |
| 10580042 |
Energy-efficient content serving |
Suman Kumar Nath, Oriana Riva, Prashanth Mohan |
2020-03-03 |
| 10565182 |
Hardware LZMA compressor |
Scott A. Hauck |
2020-02-18 |
| 10540588 |
Deep neural network processing on hardware accelerators with stacked memory |
Derek Chiou, Eric S. Chung, Andrew R. Putnam |
2020-01-21 |
| 10528119 |
Dynamic power routing to hardware accelerators |
Andrew R. Putnam, Stephen F. Heil, Eric S. Chung, Adrian M. Caulfield |
2020-01-07 |
