Issued Patents 2020
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10879255 | Apparatuses including memory arrays with source contacts adjacent edges of sources | — | 2020-12-29 |
| 10854293 | Segmented memory operation | Han Zhao | 2020-12-01 |
| 10824336 | Sequential memory access operations | — | 2020-11-03 |
| 10796778 | Apparatuses and methods to control body potential in 3D non-volatile memory operations | Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu +2 more | 2020-10-06 |
| 10784269 | Memory device including pass transistors in memory tiers | — | 2020-09-22 |
| 10770470 | Memory array having connections going through control gates | Tamotsu Murakoshi, Deepak Thimmegowda | 2020-09-08 |
| 10748918 | Methods of forming semiconductor device structures including staircase structures | — | 2020-08-18 |
| 10741259 | Apparatuses and methods using dummy cells programmed to different states | Aaron Yip | 2020-08-11 |
| 10734049 | Apparatuses and methods involving accessing distributed sub-blocks of memory cells | — | 2020-08-04 |
| 10706895 | Interconnections for 3D memory | — | 2020-07-07 |
| 10692870 | Three-dimensional devices having reduced contact length | — | 2020-06-23 |
| 10685721 | Apparatuses and methods for charging a global access line prior to accessing a memory | — | 2020-06-16 |
| 10672477 | Segmented memory and operation | Han Zhao | 2020-06-02 |
| 10580502 | Memory read apparatus and methods | — | 2020-03-03 |
| 10580790 | Semiconductor apparatus with multiple tiers, and methods | — | 2020-03-03 |
| 10573728 | Field effect transistors having a fin | — | 2020-02-25 |