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Memory device with reduced capacitance |
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Channel conductivity in memory structures |
Prashant Majhi, Khaled Hasnat |
2020-12-01 |
| 10847234 |
Program verify technique for non-volatile memory |
Han Zhao, Richard Fastow, Arun Thathachary, Narayanan Ramanan |
2020-11-24 |
| 10847233 |
Memory devices and apparatus configured to apply positive voltage levels to data lines for memory cells selected for and inhibited from programming |
Akira Goda, Yijie Zhao |
2020-11-24 |
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Non-volatile memory with storage nodes having a radius of curvature |
Randy J. Koval, Henok T. MEBRAHTU |
2020-11-03 |
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Multi-decks memory device including inter-deck switches |
Benben Li, Akira Goda, Ramey M. Abdelrahaman, Ian C. Laboriante |
2020-11-03 |
| 10796778 |
Apparatuses and methods to control body potential in 3D non-volatile memory operations |
Han Zhao, Akira Goda, Aurelio Giancarlo Mauri, Haitao Liu, Toru Tanzawa +2 more |
2020-10-06 |
| 10784274 |
3-dimensional flash memory with increased floating gate length |
Rahul Agarwal, Srivardhan Gowda |
2020-09-22 |
| 10783967 |
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Akira Goda, Shafqat Ahmed, Khaled Hasnat |
2020-09-22 |
| 10699790 |
Erase and soft program for vertical NAND flash |
Pranav Kalavade, Koichi Kawai, Akira Goda |
2020-06-30 |
| 10658285 |
Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells |
Sanh D. Tang, Roger W. Lindsay |
2020-05-19 |
| 10658053 |
Ramping inhibit voltage during memory programming |
Shantanu R. Rajwade, Pranav Kalavade, Neal R. Mielke, Shyam Sunder Raghunathan |
2020-05-19 |
| 10629271 |
Method and system for reducing program disturb degradation in flash memory |
Han Zhao, Pranav Kalavade |
2020-04-21 |
| 10622450 |
Modified floating gate and dielectric layer geometry in 3D memory arrays |
Randy J. Koval, Srikant Jayanti, Hiroyuki Sanda, Meng-Wei Kuo, Srivardhan Gowda |
2020-04-14 |
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Cell pillar structures and integrated flows |
Fatma Arzum Simsek-Ege |
2020-01-07 |
