Issued Patents 2020
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10846054 | Underflow/overflow detection prior to normalization | Son T. Dao | 2020-11-24 |
| 10846053 | Underflow/overflow detection prior to normalization | Son T. Dao | 2020-11-24 |
| 10740098 | Aligning most significant bits of different sized elements in comparison result vectors | Cedric Lichtenau, Jens Seifert, Jörg-Stephan Vogt, Markus Lachenmayr, L'Emir Salim Chehab +2 more | 2020-08-11 |
| 10713056 | Wide vector execution in single thread mode for an out-of-order processor | Mauricio J. Serrano, Balaram Sinharoy | 2020-07-14 |
| 10705847 | Wide vector execution in single thread mode for an out-of-order processor | Mauricio J. Serrano, Balaram Sinharoy | 2020-07-07 |
| 10656913 | Enhanced low precision binary floating-point formatting | Ankur Agrawal, Bruce M. Fleischer, Kailash Gopalakrishnan, Dongsoo Lee | 2020-05-19 |
| 10649738 | Combined residue circuit protecting binary and decimal data | Steven R. Carlough, Klaus M. Kroener, Andreas Wagner | 2020-05-12 |
| 10649730 | Normalization of a product on a datapath | Klaus M. Kroener, Cedric Lichtenau, Andreas Wagner | 2020-05-12 |
| 10592208 | Very low precision floating point representation for deep learning acceleration | Naigang Wang, Kailash Gopalakrishnan, Jungwook Choi, Ankur Agrawal, Daniel Brand | 2020-03-17 |
| 10579375 | Method to build reconfigurable variable length comparators | Cedric Lichtenau, Jens Seifert, Jörg-Stephan Vogt, Markus Lachenmayr, L'Emir Salim Chehab +2 more | 2020-03-03 |
| 10572223 | Parallel decimal multiplication hardware with a 3x generator | Steven R. Carlough, Michael Klein, Michael K. Kroener | 2020-02-25 |
| 10558432 | Multiply-add operations of binary numbers in an arithmetic unit | Tina Babinsky, Michael Klein, Cedric Lichtenau | 2020-02-11 |