Issued Patents 2020
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10802829 | Scalable dependency matrix with wake-up columns for long latency instructions in an out-of-order processor | Joel A. Silberman | 2020-10-13 |
| 10776113 | Executing load-store operations without address translation hardware per load-store unit port | Christopher Gonzalez, Bryan Lloyd | 2020-09-15 |
| 10713056 | Wide vector execution in single thread mode for an out-of-order processor | Silvia M. Mueller, Mauricio J. Serrano | 2020-07-14 |
| 10705847 | Wide vector execution in single thread mode for an out-of-order processor | Silvia M. Mueller, Mauricio J. Serrano | 2020-07-07 |
| 10628158 | Executing load-store operations without address translation hardware per load-store unit port | Christopher Gonzalez, Bryan Lloyd | 2020-04-21 |
| 10628166 | Allocating and deallocating reorder queue entries for an out-of-order processor | Bryan Lloyd | 2020-04-21 |
| 10606591 | Handling effective address synonyms in a load-store unit that operates without address translation | Bryan Lloyd | 2020-03-31 |
| 10606590 | Effective address based load store unit in out of order processors | Bryan Lloyd | 2020-03-31 |
| 10606592 | Handling effective address synonyms in a load-store unit that operates without address translation | Bryan Lloyd | 2020-03-31 |
| 10606593 | Effective address based load store unit in out of order processors | Bryan Lloyd | 2020-03-31 |
| 10579387 | Efficient store-forwarding with partitioned FIFO store-reorder queue in out-of-order processor | Christopher Gonzalez, Bryan Lloyd | 2020-03-03 |
| 10579384 | Effective address based instruction fetch unit for out of order processors | Robert Alan Philhower | 2020-03-03 |
| 10572256 | Handling effective address synonyms in a load-store unit that operates without address translation | Bryan Lloyd | 2020-02-25 |
| 10572264 | Completing coalesced global completion table entries in an out-of-order processor | Joel A. Silberman | 2020-02-25 |
| 10572257 | Handling effective address synonyms in a load-store unit that operates without address translation | Bryan Lloyd | 2020-02-25 |
| 10564979 | Coalescing global completion table entries in an out-of-order processor | Joel A. Silberman | 2020-02-18 |
| 10564976 | Scalable dependency matrix with multiple summary bits in an out-of-order processor | Joel A. Silberman | 2020-02-18 |
| 10534616 | Load-hit-load detection in an out-of-order processor | Christopher Gonzalez, Bryan Lloyd | 2020-01-14 |