Issued Patents 2020
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10879357 | Method for making a semiconductor device having a hyper-abrupt junction region including a superlattice | Richard Burton, Robert J. Mears | 2020-12-29 |
| 10868120 | Method for making a varactor with hyper-abrupt junction region including a superlattice | Richard Burton, Robert J. Mears | 2020-12-15 |
| 10854717 | Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistance | Hideki Takeuchi, Daniel J. Connelly, Richard Burton, Robert J. Mears | 2020-12-01 |
| 10847618 | Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistance | Hideki Takeuchi, Daniel J. Connelly, Richard Burton, Robert J. Mears | 2020-11-24 |
| 10840336 | Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methods | Daniel J. Connelly, Hideki Takeuchi, Richard Burton, Robert J. Mears | 2020-11-17 |
| 10840388 | Varactor with hyper-abrupt junction region including a superlattice | Richard Burton, Robert J. Mears | 2020-11-17 |
| 10840337 | Method for making a FINFET having reduced contact resistance | Hideki Takeuchi, Daniel J. Connelly, Richard Burton, Robert J. Mears | 2020-11-17 |
| 10840335 | Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistance | Hideki Takeuchi, Daniel J. Connelly, Richard Burton, Robert J. Mears | 2020-11-17 |
| 10825902 | Varactor with hyper-abrupt junction region including spaced-apart superlattices | Richard Burton, Robert J. Mears | 2020-11-03 |
| 10825901 | Semiconductor devices including hyper-abrupt junction region including a superlattice | Richard Burton, Robert J. Mears | 2020-11-03 |
| 10818755 | Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance | Hideki Takeuchi, Daniel J. Connelly, Richard Burton, Robert J. Mears | 2020-10-27 |
| 10811498 | Method for making superlattice structures with reduced defect densities | Keith Doran Weeks, Nyles Wynn Cody, Robert J. Mears, Robert John Stephenson | 2020-10-20 |
| 10727049 | Method for making a semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice | Keith Doran Weeks, Nyles Wynn Cody, Robert J. Mears, Robert John Stephenson | 2020-07-28 |
| 10593761 | Method for making a semiconductor device having reduced contact resistance | Hideki Takeuchi, Daniel J. Connelly, Richard Burton, Robert J. Mears | 2020-03-17 |
| 10580867 | FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistance | Hideki Takeuchi, Daniel J. Connelly, Richard Burton, Robert J. Mears | 2020-03-03 |
| 10580866 | Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance | Hideki Takeuchi, Daniel J. Connelly, Richard Burton, Robert J. Mears | 2020-03-03 |
| 10566191 | Semiconductor device including superlattice structures with reduced defect densities | Keith Doran Weeks, Nyles Wynn Cody, Robert J. Mears, Robert John Stephenson | 2020-02-18 |