Issued Patents 2020
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10852354 | System and method for accelerating real X detection in gate-level logic simulation | — | 2020-12-01 |
| 10794954 | System and method for accelerating timing-accurate gate-level logic simulation | Hong-zu Chou, Yueh-Shiuan Tsai | 2020-10-06 |
| 10740521 | System and method for localized logic simulation replay using emulated values | Christopher S. Browy | 2020-08-11 |
| 10726180 | Systems and methods for fixing X-pessimism from uninitialized latches in gate-level simulation | Andrew Christopher Stein, Hong-zu Chou, Christopher S. Browy, Chi-Lai Huang | 2020-07-28 |
| 10666255 | System and method for compacting X-pessimism fixes for gate-level logic simulation | Hong-zu Chou | 2020-05-26 |