Issued Patents 2020
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10838860 | Memory-mapped interface to message-passing computing systems | Filipp A. Akopyan, John V. Arthur, Andrew S. Cassidy, Michael Vincent DeBole, Paul A. Merolla +1 more | 2020-11-17 |
| 10834024 | Selective multicast delivery on a bus-based interconnect | Simon James Hollis, Hartmut Penner, Andrew S. Cassidy, Pallab Datta | 2020-11-10 |
| 10831595 | Performing error detection during deterministic program execution | Andrew S. Cassidy, Dharmendra S. Modha, John V. Arthur | 2020-11-10 |
| 10785745 | Scaling multi-core neurosynaptic networks across chip boundaries | Rodrigo Alvarez Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla +1 more | 2020-09-22 |
| 10769519 | Converting digital numeric data to spike event data | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Steven K. Esser, Myron D. Flickner +4 more | 2020-09-08 |
| 10755165 | Converting spike event data to digital numeric data | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Steven K. Esser, Myron D. Flickner +4 more | 2020-08-25 |
| 10740282 | Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer +3 more | 2020-08-11 |
| 10650301 | Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation | Rodrigo Alvarez-Icaza Rivera, Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson +2 more | 2020-05-12 |
| 10621489 | Massively parallel neural inference computing elements | Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy, Pallab Datta, Steven K. Esser +5 more | 2020-04-14 |