Issued Patents 2020
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10878313 | Post synaptic potential-based learning rule | Charles Augustine, Somnath Paul, Sadique Ul Ameen Sheik | 2020-12-29 |
| 10784874 | All-digital voltage monitor (ADVM) with single-cycle latency | Suyoung Bang, Eric C. Samson, Wootaek Lim, Charles Augustine | 2020-09-22 |
| 10784865 | Minimum delay error detection and correction for pulsed latches | Pascal A. Meinerzhagen, Vivek K. De | 2020-09-22 |
| 10755771 | Techniques for multi-read and multi-write of memory circuit | Somnath Paul, Charles Augustine, Turbo Majumder, Suyoung Bang | 2020-08-25 |
| 10748060 | Pre-synaptic learning using delayed causal updates | Somnath Paul, Charles Augustine | 2020-08-18 |
| 10707877 | Method and apparatus for switched adaptive clocking | Turbo Majumder, Minki Cho, Carlos Tokunaga, Praveen Mosalikanti, Nasser A. Kurd | 2020-07-07 |
| 10698432 | Dual loop digital low drop regulator and current sharing control apparatus for distributable voltage regulators | Yi-Chun Shih, Kaushik Mazumdar, Stephen Kim, Rinkle Jain, James W. Tschanz | 2020-06-30 |
| 10685688 | Low swing bitline for sensing arrays | Jaydeep P. Kulkarni | 2020-06-16 |
| 10666259 | Current steering level-shifter | Andres Malavasi Mora, Jaydeep P. Kulkarni, Anupama A. Thaploo | 2020-05-26 |
| 10665222 | Method and system of temporal-domain feature extraction for automatic speech recognition | Suyoung Bang, Somnath Paul, Charles Augustine, Turbo Majumder, Wootaek Lim +2 more | 2020-05-26 |
| 10635968 | Technologies for memory management of neural networks with sparse connectivity | Somnath Paul, Charles Augustine, Sadique Ul Ameen Sheik | 2020-04-28 |
| 10528473 | Disabling cache portions during low voltage operations | Christopher B. Wilkerson, Vivek K. De, Ming Zhang, Jaume Abella, Javier Carretero Casado +3 more | 2020-01-07 |