Issued Patents 2020
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10621092 | Merging level cache and data cache units having indicator bits related to speculative execution | Fernando Latorre, Josep M. Codina, Enric Gibert Codina, Pedro Lopez, Carlos Madriles +2 more | 2020-04-14 |
| 10528473 | Disabling cache portions during low voltage operations | Christopher B. Wilkerson, Muhammad M. Khellah, Vivek K. De, Ming Zhang, Jaume Abella +3 more | 2020-01-07 |