Issued Patents 2020
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10877864 | Controlling segment layout in a stress test for a processor memory with a link stack | Shakti Kapoor | 2020-12-29 |
| 10831620 | Core pairing in multicore systems | Prasanna Jayaraman, Rahul M. Rao | 2020-11-10 |
| 10748637 | System and method for testing processor errors | Nelson Wu, Shakti Kapoor, Nandhini Rajaiah | 2020-08-18 |
| 10713179 | Efficiently generating effective address translations for memory management test cases | Shakti Kapoor | 2020-07-14 |
| 10540249 | Stress testing a processor memory with a link stack | Shakti Kapoor | 2020-01-21 |