YK

Yael Kinderman

CS Cadence Design Systems: 2 patents #41 of 328Top 15%
Overall (2020): #106,069 of 565,922Top 20%
2
Patents 2020

Issued Patents 2020

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
10607039 Constrained metric optimization of a system on chip Shlomi Uziel, Ido Avraham, Michele Petracca, Yosinori Watanabe 2020-03-31
10586014 Method and system for verification using combined verification data David R. Spatafore, Nili Segal, Yan Yagudayev, Vincent Gregory Reynolds 2020-03-10