Issued Patents 2020
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10853546 | Method and system for sequential equivalence checking | Yaron Schiller, Almothana Sirhan, Karam Abdelkader, Thiago Radicchi Roque | 2020-12-01 |
| 10789404 | System, method, and computer program product for generating a formal verification model | Rajdeep Mukherjee, Benjamin Chen, Ziyad Hanna | 2020-09-29 |
| 10782767 | System, method, and computer program product for clock gating in a formal verification | Karam Abd Elkader, Doron Bustan, Yaron Schiller | 2020-09-22 |
| 10546083 | System, method, and computer program product for improving coverage accuracy in formal verification | Amit Verma, Suyash Kumar | 2020-01-28 |