Issued Patents 2020
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10867978 | Integrated circuit module with integrated discrete devices | Rahul Agarwal | 2020-12-15 |
| 10825692 | Semiconductor chip gettering | Rahul Agarwal, Ivor G. Barber, Venkatachalam Valliappan, Yuen Ting Cheng, Guan Sin Chok | 2020-11-03 |
| 10727204 | Die stacking for multi-tier 3D integration | Rahul Agarwal | 2020-07-28 |
| 10714462 | Multi-chip package with offset 3D structure | Rahul Agarwal, Gabriel H. Loh | 2020-07-14 |
| 10672712 | Multi-RDL structure packages and methods of fabricating the same | Lei Fu, Farshad Ghahghahi | 2020-06-02 |
| 10655988 | Watch with rotatable optical encoder having a spindle defining an array of alternating regions extending along an axial direction parallel to the axis of a shaft | Paisith P. Boonsom, Serhan O. Isikman, Richard Ruh, Prashanth S. Holenarsipur, Colin M. Ely +5 more | 2020-05-19 |
| 10593628 | Molded die last chip combination | Rahul Agarwal | 2020-03-17 |
| 10593620 | Fan-out package with multi-layer redistribution layer structure | Rahul Agarwal, Priyal Shah | 2020-03-17 |
| 10573630 | Offset-aligned three-dimensional integrated circuit | Brett P. Wilkerson, Rahul Agarwal, Dmitri Yudanov | 2020-02-25 |
| 10529693 | 3D stacked dies with disparate interconnect footprints | Rahul Agarwal | 2020-01-07 |