Issued Patents 2019
Showing 1–25 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10515302 | Neural network unit with mixed data and weight size computation capability | Kim C. Houck | 2019-12-24 |
| 10509765 | Neural processing unit that selectively writes back to neural memory either activation function output or accumulator value | Terry Parks | 2019-12-17 |
| 10474627 | Neural network unit with neural memory and array of neural processing units that collectively shift row of data received from neural memory | Terry Parks | 2019-11-12 |
| 10474628 | Processor with variable rate execution unit | Terry Parks | 2019-11-12 |
| 10438115 | Neural network unit with memory layout to perform efficient 3-dimensional convolutions | Kim C. Houck | 2019-10-08 |
| 10430706 | Processor with memory array operable as either last level cache slice or neural network unit memory | Douglas R. Reed | 2019-10-01 |
| 10423876 | Processor with memory array operable as either victim cache or neural network unit memory | Douglas R. Reed | 2019-09-24 |
| 10423216 | Asymmetric multi-core processor with native switching mechanism | Rodney E. Hooker, Terry Parks | 2019-09-24 |
| 10417560 | Neural network unit that performs efficient 3-dimensional convolutions | Kim C. Houck | 2019-09-17 |
| 10409767 | Neural network unit with neural memory and array of neural processing units and sequencer that collectively shift row of data received from neural memory | Terry Parks | 2019-09-10 |
| 10409347 | Domain-differentiated power state coordination system | Darius D. Gaskins | 2019-09-10 |
| 10394562 | Microprocessor that fuses if-then instructions | Terry Parks | 2019-08-27 |
| 10395165 | Neural network unit with neural memory and array of neural processing units that collectively perform multi-word distance rotates of row of data received from neural memory | Kim C. Houck | 2019-08-27 |
| 10387366 | Neural network unit with shared activation function units | Terry Parks | 2019-08-20 |
| 10380064 | Neural network unit employing user-supplied reciprocal for normalizing an accumulated value | Terry Parks | 2019-08-13 |
| 10380481 | Neural network unit that performs concurrent LSTM cell calculations | Terry Parks, Kyle T. O'Brien | 2019-08-13 |
| 10366050 | Multi-operation neural network unit | Terry Parks | 2019-07-30 |
| 10353862 | Neural network unit that performs stochastic rounding | Terry Parks | 2019-07-16 |
| 10353860 | Neural network unit with neural processing units dynamically configurable to process multiple data sizes | Terry Parks | 2019-07-16 |
| 10353861 | Mechanism for communication between architectural program running on processor and non-architectural program running on execution unit of the processor regarding shared resource | Terry Parks | 2019-07-16 |
| 10346351 | Neural network unit with output buffer feedback and masking capability with processing unit groups that operate as recurrent neural network LSTM cells | Terry Parks, Kyle T. O'Brien | 2019-07-09 |
| 10346350 | Direct execution by an execution unit of a micro-operation loaded into an architectural register file by an architectural instruction of a processor | Terry Parks | 2019-07-09 |
| 10282348 | Neural network unit with output buffer feedback and masking capability | Terry Parks, Kyle T. O'Brien | 2019-05-07 |
| 10275393 | Tri-configuration neural network unit | Terry Parks | 2019-04-30 |
| 10275394 | Processor with architectural neural network execution unit | Terry Parks | 2019-04-30 |