Issued Patents 2019
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10509765 | Neural processing unit that selectively writes back to neural memory either activation function output or accumulator value | G. Glenn Henry | 2019-12-17 |
| 10474628 | Processor with variable rate execution unit | G. Glenn Henry | 2019-11-12 |
| 10474627 | Neural network unit with neural memory and array of neural processing units that collectively shift row of data received from neural memory | G. Glenn Henry | 2019-11-12 |
| 10423216 | Asymmetric multi-core processor with native switching mechanism | Rodney E. Hooker, G. Glenn Henry | 2019-09-24 |
| 10409767 | Neural network unit with neural memory and array of neural processing units and sequencer that collectively shift row of data received from neural memory | G. Glenn Henry | 2019-09-10 |
| 10394562 | Microprocessor that fuses if-then instructions | G. Glenn Henry | 2019-08-27 |
| 10387366 | Neural network unit with shared activation function units | G. Glenn Henry | 2019-08-20 |
| 10380064 | Neural network unit employing user-supplied reciprocal for normalizing an accumulated value | G. Glenn Henry | 2019-08-13 |
| 10380481 | Neural network unit that performs concurrent LSTM cell calculations | G. Glenn Henry, Kyle T. O'Brien | 2019-08-13 |
| 10366050 | Multi-operation neural network unit | G. Glenn Henry | 2019-07-30 |
| 10353861 | Mechanism for communication between architectural program running on processor and non-architectural program running on execution unit of the processor regarding shared resource | G. Glenn Henry | 2019-07-16 |
| 10353860 | Neural network unit with neural processing units dynamically configurable to process multiple data sizes | G. Glenn Henry | 2019-07-16 |
| 10353862 | Neural network unit that performs stochastic rounding | G. Glenn Henry | 2019-07-16 |
| 10346350 | Direct execution by an execution unit of a micro-operation loaded into an architectural register file by an architectural instruction of a processor | G. Glenn Henry | 2019-07-09 |
| 10346351 | Neural network unit with output buffer feedback and masking capability with processing unit groups that operate as recurrent neural network LSTM cells | G. Glenn Henry, Kyle T. O'Brien | 2019-07-09 |
| 10282348 | Neural network unit with output buffer feedback and masking capability | G. Glenn Henry, Kyle T. O'Brien | 2019-05-07 |
| 10275394 | Processor with architectural neural network execution unit | G. Glenn Henry | 2019-04-30 |
| 10275393 | Tri-configuration neural network unit | G. Glenn Henry | 2019-04-30 |
| 10268586 | Processor with programmable prefetcher operable to generate at least one prefetch address based on load requests | G. Glenn Henry, Rodney E. Hooker, Douglas R. Reed | 2019-04-23 |
| 10268587 | Processor with programmable prefetcher operable to generate at least one prefetch address based on load requests | G. Glenn Henry, Rodney E. Hooker, Douglas R. Reed | 2019-04-23 |
| 10235232 | Processor with approximate computing execution unit that includes an approximation control register having an approximation mode flag, an approximation amount, and an error threshold, where the approximation control register is writable by an instruction set instruction | G. Glenn Henry, Rodney E. Hooker | 2019-03-19 |
| 10228911 | Apparatus employing user-specified binary point fixed point arithmetic | G. Glenn Henry | 2019-03-12 |
| 10216520 | Compressing instruction queue for a microprocessor | Matthew Daniel Day, G. Glenn Henry | 2019-02-26 |
| 10198269 | Dynamic reconfiguration of multi-core processor | G. Glenn Henry, Darius D. Gaskins | 2019-02-05 |