Issued Patents 2019
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10511314 | Frequency generator and associated method | Chia-Chun Liao, Min-Shueh Yuan, Chao Li | 2019-12-17 |
| 10447285 | Software reconfigurable digital phase lock loop architecture | Roman Staszewki, Fuqiang Shi | 2019-10-15 |
| 10340940 | Variable step switched capacitor based digital to analog converter incorporating higher order interpolation | Sushrant Monga | 2019-07-02 |
| 10326454 | All-digital phase locked loop using switched capacitor voltage doubler | Feng-Wei Kuo, Chewn-Pu Jou, Huan-Neng Chen, Lan-Chou Cho, Seyednaser Pourmousavian | 2019-06-18 |
| 10326491 | Transceiving device | Feng-Wei Kuo, Huan-Neng Chen, Lan-Chou Cho, Chewn-Pu Jou, Masoud Babaie | 2019-06-18 |
| 10303124 | Time-to-digital converter | Ying-Cheng Wu, Yihong Mao | 2019-05-28 |
| 10291179 | Oscillator and clock generator | Chao Li | 2019-05-14 |
| 10277117 | Device with a voltage multiplier | Yu-Tso Lin, Chih-Hsien Chang, Min-Shueh Yuan, Seyednaser Pourmousavian | 2019-04-30 |
| 10270487 | Frequency generator and associated method | Chia-Chun Liao, Min-Shueh Yuan, Chao Li | 2019-04-23 |
| 10270486 | Ultra-low power receiver | Feng-Wei Kuo, Chewn-Pu Jou, Huan-Neng Chen, Lan-Chou Cho, Sandro Binsfeld Ferreira | 2019-04-23 |
| 10171089 | PVT-free calibration function using a doubler circuit for TDC resolution in ADPLL applications | Feng-Wei Kuo, Chewn-Pu Jou, Lan-Chou Cho, Huan-Neng Chen, Seyednaser Pourmousavian | 2019-01-01 |