Issued Patents 2019
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10510413 | Multi-pass programming with modified pass voltages to tighten threshold voltage distributions | Vinh Diep | 2019-12-17 |
| 10482981 | Preventing refresh of voltages of dummy memory cells to reduce threshold voltage downshift for select gate transistors | Vinh Diep | 2019-11-19 |
| 10446244 | Adjusting voltage on adjacent word line during verify of memory cells on selected word line in multi-pass programming | Vinh Diep, Zhengyi Zhang, Yingda Dong | 2019-10-15 |
| 10373697 | Programming dummy memory cells in erase operation to reduce threshold voltage downshift for select gate transistors | Chun-Hung Lai, Rajdeep Gautam, Shih-Chung Lee | 2019-08-06 |
| 10276248 | Early ramp down of dummy word line voltage during read to suppress select gate transistor downshift | Vinh Diep | 2019-04-30 |
| 10256137 | Self-aligned trench isolation in integrated circuits | Lei Xue, Kenichi Ohtsuka, Simon S. Chan, Rinji Sugino | 2019-04-09 |
| 10249372 | Reducing hot electron injection type of read disturb in 3D memory device during signal switching transients | Hong-Yan Chen, Wei Zhao, Yingda Dong | 2019-04-02 |
| 10235294 | Pre-read voltage pulse for first read error handling | Swaroop Kaza, Piyush Sagdeo | 2019-03-19 |
| 10204689 | Non-volatile memory with methods to reduce creep-up field between dummy control gate and select gate | Anubhav Khandelwal, Changyuan Chen, Cynthia Hsu, Yingda Dong | 2019-02-12 |