| 10503660 |
Technique for determining address translation data to be stored within an address translation cache |
Abhishek Raja |
2019-12-10 |
| 10402349 |
Memory controller having data access hint message for specifying the given range of one or more memory addresses |
Jamshed Jalal, Klas Magnus Bruce, Paul Gilbert Meyer, David Joseph Hawkins, Phanindra Kumar Mannava +1 more |
2019-09-03 |
| 10310862 |
Data processing |
Robert G. McDonald, Glen Andrew Harris |
2019-06-04 |
| 10289417 |
Branch prediction suppression for blocks of instructions predicted to not include a branch instruction |
Matthew Paul Elwood, Umar Farooq, Adam George |
2019-05-14 |
| 10268581 |
Cache hierarchy management |
Klas Magnus Bruce, Vasu Kudaravalli, Adam George, Muhammad Umar Farooq, Joseph Michael Pusdesris |
2019-04-23 |
| 10229066 |
Queuing memory access requests |
Miles Robert Dooley, Matthew A. Rafacz, Huzefa Sanjeliwala |
2019-03-12 |
| 10185663 |
Cache bypass |
Jamshed Jalal, Bruce James Mathewson, Phanindra Kumar Mannava |
2019-01-22 |
| 10176104 |
Instruction predecoding |
Vasu Kudaravalli, Matthew Paul Elwood, Adam George, Muhammad Umar Farooq |
2019-01-08 |