Issued Patents 2019
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10489323 | Data processing system for a home node to authorize a master to bypass the home node to directly send data to a slave | Guanghui Geng, Andrew David Tune, Daniel Sara, Phanindra Kumar Mannava, Bruce James Mathewson | 2019-11-26 |
| 10489315 | Dynamic adaptation of direct memory transfer in a data processing system with mismatched data-bus widths | Tushar P. Ringe, Phanindra Kumar Mannava, Mark David Werkheiser, Ramamoorthy Guru Prasadh, Gurunath Ramagiri | 2019-11-26 |
| 10452575 | System, method and apparatus for ordering logic | Tushar P. Ringe, Mark David Werkheiser, Glenn Allan Canto, Ashok Kumar Tummala, Devi Sravanthi Yalamarthy | 2019-10-22 |
| 10452593 | High-performance streaming of ordered write stashes to enable optimized data sharing between I/O masters and CPUs | Tushar P. Ringe, Ashok Kumar Tummala, Gurunath Ramagiri | 2019-10-22 |
| 10423466 | Optimized streaming in an un-ordered interconnect | Ashok Kumar Tummala, Paul Gilbert Meyer, Dimitrios Kaseridis | 2019-09-24 |
| 10402349 | Memory controller having data access hint message for specifying the given range of one or more memory addresses | Michael Filippo, Klas Magnus Bruce, Paul Gilbert Meyer, David Joseph Hawkins, Phanindra Kumar Mannava +1 more | 2019-09-03 |
| 10310979 | Snoop filter for cache coherency in a data processing system | Mark David Werkheiser | 2019-06-04 |
| 10282297 | Read-with overridable-invalidate transaction | Phanindra Kumar Mannava, Bruce James Mathewson, Mark David Werkheiser | 2019-05-07 |
| 10185663 | Cache bypass | Michael Filippo, Bruce James Mathewson, Phanindra Kumar Mannava | 2019-01-22 |