Issued Patents 2019
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10451676 | Method and system for dynamic standard test access (DSTA) for a logic block reuse | Milind Sonawane, Amit Sanghani, Shantanu Sarangi, Bala Tarun Nelapatla, Sailendra Chadalavda +3 more | 2019-10-22 |
| 10444280 | Independent test partition clock coordination across multiple test partitions | Dheepakkumaran Jayaraman, Karthikeyan Natarajan, Shantanu Sarangi, Amit Sanghani, Milind Sonawane +4 more | 2019-10-15 |
| 10317463 | Scan system interface (SSI) module | Milind Sonawane, Amit Sanghani, Rajendra Kumar reddy.S, Bala Tarun Nelapatla, Sailendra Chadalavda +1 more | 2019-06-11 |
| 10281524 | Test partition external input/output interface control for test partitions in a semiconductor | Sailendra Chadalavda, Shantanu Sarangi, Milind Sonawane, Amit Sanghani, Dan Tobin Smith +2 more | 2019-05-07 |