Issued Patents 2019
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10509073 | Timing-aware test generation and fault simulation | Xijiang Lin, Mark Kassab, Chen Wang, Janusz Rajski | 2019-12-17 |
| 10317462 | Wide-range clock signal generation for speed grading of logic cores | Shi-Yu Huang, Wu-Tung Cheng, Tzu-Heng Huang | 2019-06-11 |