Issued Patents 2019
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10467008 | Identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor | Mehul Patel, Albert J. Van Norstrand, Jr., Phillip G. Williams | 2019-11-05 |
| 10379857 | Dynamic sequential instruction prefetching | Richard J. Eickemeyer, Sheldon B. Levenstein, Mauricio J. Serrano, Brian W. Thompto | 2019-08-13 |
| 10353710 | Techniques for predicting a target address of an indirect branch instruction | Richard J. Eickemeyer, Naga P. Gorti, Albert J. Van Norstrand, Jr. | 2019-07-16 |
| 10275256 | Branch prediction in a computer processor | Bruce M. Fleischer, Michael N. Goulet, Nicholas R. Orzol | 2019-04-30 |
| 10248555 | Managing an effective address table in a multi-slice processor | Akash V. Giri, Mehul Patel, Albert J. Van Norstrand, Jr. | 2019-04-02 |
| 10241905 | Managing an effective address table in a multi-slice processor | Akash V. Giri, Mehul Patel, Albert J. Van Norstrand, Jr. | 2019-03-26 |
| 10175987 | Instruction prefetching in a computer processor using a prefetch prediction vector | Richard J. Eickemeyer, Sheldon B. Levenstein, Mauricio J. Serrano | 2019-01-08 |