Issued Patents 2019
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10491217 | Low-power clock gate circuit | Steven Hsu, Amit Agarwal, Simeon Realov, Ram Krishnamurthy | 2019-11-26 |
| 10409319 | System, apparatus and method for providing a local clock signal for a memory array | Altug Koker, Bhushan M. Borole, Kamal Sinha, Abhishek R. Appu, Anupama A. Thaploo +2 more | 2019-09-10 |
| 10347324 | System, apparatus and method for segmenting a memory array | Bhushan M. Borole, Anupama A. Thaploo, Sunil Nekkanti, Altug Koker, Abhisek R. Appu | 2019-07-09 |
| 10333379 | Power switching circuitry including power-up control | Suphachai Chai Sutanthavibul, Anupama A. Thaploo, Surya Sasi Kiran Tallapragada, Daivik H Bhatt, Lei Jiang +3 more | 2019-06-25 |
| 10324721 | Reducing aging of register file keeper circuits | Anupama A. Thaploo, Bhushan M. Borole, Bee Ngo, Altug Koker, Abhishek R. Appu +2 more | 2019-06-18 |
| 10193536 | Shared keeper and footer flip-flop | Amit Agarwal, Steven Hsu, Simeon Realov, Ram Krishnamurthy | 2019-01-29 |
| 10177765 | Integrated clock gate circuit with embedded NOR | Steven Hsu, Amit Agarwal, Simeon Realov, Ram Krishnamurthy | 2019-01-08 |