Issued Patents 2019
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10374584 | Low power retention flip-flop with level-sensitive scan circuitry | Charles Augustine, Muhammad M. Khellah, Feroze Merchant, Ashish V. Choubal | 2019-08-06 |
| 10261572 | Technologies for managing power during an activation cycle | Aswin Ramachandran | 2019-04-16 |
| 10198065 | Selecting a low power state based on cache flush latency determination | Sundar Ramani, Arvind Mandhani, Ashish V. Choubal, Kalyan Muthukumar, Ajaya V. Durg +1 more | 2019-02-05 |