Issued Patents 2019
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10394711 | Managing lowest point of coherency (LPC) memory using a service layer adapter | Etai Adar, Yiftach Benjamini, Bartholomew Blaner, William J. Starke, Jeffrey A. Stuecheli | 2019-08-27 |
| 10346164 | Memory move instruction sequence targeting an accelerator switchboard | Bartholomew Blaner, William J. Starke, Randal C. Swanberg, Scott M. Willenborg | 2019-07-09 |
| 10289479 | Hardware accelerator address translation fault resolution | Richard Louis Arndt, Bartholomew Blaner | 2019-05-14 |
| 10235215 | Memory lock mechanism for a multiprocessor system | Ravi Kumar Arimilli, Guy L. Guthrie, William J. Starke | 2019-03-19 |
| 10216653 | Pre-transmission data reordering for a serial interface | Yiftach Benjamini, Bartholomew Blaner, Daniel M. Dreps, John D. Irish, David J. Krolak +6 more | 2019-02-26 |
| 10216568 | Live partition mobility enabled hardware accelerator address translation fault resolution | Richard Louis Arndt, Bartholomew Blaner | 2019-02-26 |
| 10169247 | Direct memory access between an accelerator and a processor using a coherency adapter | Etai Adar, Yiftach Benjamini | 2019-01-01 |