YW

Yosinori Watanabe

CS Cadence Design Systems: 4 patents #15 of 394Top 4%
📍 Lafayette, CA: #9 of 94 inventorsTop 10%
🗺 California: #6,166 of 67,890 inventorsTop 10%
Overall (2019): #40,034 of 560,194Top 8%
4
Patents 2019

Issued Patents 2019

Showing 1–4 of 4 patents

Patent #TitleCo-InventorsDate
10423741 Constrained metric verification analysis of a system on chip Michele Petracca, Yael Kinderman, Shlomi Uziel, Ido Avraham 2019-09-24
10409939 Statistical sensitivity analyzer Michele Petracca 2019-09-10
10262088 Converting real number modeling code to cycle-driven simulation interface code for circuit design in digital mixed signal environments Ophir Turbovich 2019-04-16
10262095 Conversion of real number modeling code to cycle-driven simulation interface code for circuit design in digital mixed signal environments Ophir Turbovich 2019-04-16