MP

Michele Petracca

CS Cadence Design Systems: 2 patents #48 of 394Top 15%
📍 Chappaqua, NY: #24 of 59 inventorsTop 45%
🗺 New York: #2,767 of 13,137 inventorsTop 25%
Overall (2019): #138,450 of 560,194Top 25%
2
Patents 2019

Issued Patents 2019

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
10423741 Constrained metric verification analysis of a system on chip Yosinori Watanabe, Yael Kinderman, Shlomi Uziel, Ido Avraham 2019-09-24
10409939 Statistical sensitivity analyzer Yosinori Watanabe 2019-09-10