YK

Yael Kinderman

CS Cadence Design Systems: 2 patents #48 of 394Top 15%
Overall (2019): #105,385 of 560,194Top 20%
2
Patents 2019

Issued Patents 2019

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
10423741 Constrained metric verification analysis of a system on chip Michele Petracca, Yosinori Watanabe, Shlomi Uziel, Ido Avraham 2019-09-24
10394699 Method and system for reusing a refinement file in coverage grading Oded Oren, Yaara Gradovitch 2019-08-27