Issued Patents 2019
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10467365 | Systems and methods for calculating common clock path pessimism for hierarchical timing analysis in an electronic design | Vibhor Garg | 2019-11-05 |
| 10460059 | System and method for generating reduced standard delay format files for gate level simulation | Akash Khandelwal, Rajarshi Mukherjee, Chih-kuo Yu | 2019-10-29 |
| 10169501 | Timing context generation with multi-instance blocks for hierarchical analysis | Amit Dhuria | 2019-01-01 |