Issued Patents 2019
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10467365 | Systems and methods for calculating common clock path pessimism for hierarchical timing analysis in an electronic design | Pawan Kulshreshtha | 2019-11-05 |
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10467365 | Systems and methods for calculating common clock path pessimism for hierarchical timing analysis in an electronic design | Pawan Kulshreshtha | 2019-11-05 |