CY

Chih-kuo Yu

CS Cadence Design Systems: 1 patents #113 of 394Top 30%
📍 San Jose, CA: #2,930 of 6,652 inventorsTop 45%
🗺 California: #27,528 of 67,890 inventorsTop 45%
Overall (2019): #505,144 of 560,194Top 95%
1
Patents 2019

Issued Patents 2019

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
10460059 System and method for generating reduced standard delay format files for gate level simulation Akash Khandelwal, Pawan Kulshreshtha, Rajarshi Mukherjee 2019-10-29