Issued Patents 2019
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10366001 | Partitioning memory blocks for reducing dynamic power consumption | Chaithanya Dudha, Krishna Garlapati, Chun Zhang, Fan Zhang, Anup Kumar Sultania | 2019-07-30 |
| 10289786 | Circuit design transformation for automatic latency reduction | Chaithanya Dudha, Shangzhi Sun, Ashish Sirasao | 2019-05-14 |