Issued Patents 2019
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10430539 | Method and apparatus for enhancing performance by moving or adding a pipelined register stage in a cascaded chain | Zhao Ma, Krishna Garlapati, Ashish Sirasao | 2019-10-01 |
| 10387600 | Dynamic power reduction in circuit designs and circuits | Krishna Garlapati | 2019-08-20 |
| 10366001 | Partitioning memory blocks for reducing dynamic power consumption | Nithin Kumar Guggilla, Krishna Garlapati, Chun Zhang, Fan Zhang, Anup Kumar Sultania | 2019-07-30 |
| 10289786 | Circuit design transformation for automatic latency reduction | Shangzhi Sun, Ashish Sirasao, Nithin Kumar Guggilla | 2019-05-14 |