Issued Patents 2019
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10430539 | Method and apparatus for enhancing performance by moving or adding a pipelined register stage in a cascaded chain | Chaithanya Dudha, Zhao Ma, Ashish Sirasao | 2019-10-01 |
| 10387600 | Dynamic power reduction in circuit designs and circuits | Chaithanya Dudha | 2019-08-20 |
| 10366001 | Partitioning memory blocks for reducing dynamic power consumption | Nithin Kumar Guggilla, Chaithanya Dudha, Chun Zhang, Fan Zhang, Anup Kumar Sultania | 2019-07-30 |