Issued Patents 2018
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10073627 | Addressing, interleave, wear leveling, and initialization schemes for different chip enables and memory arrays of different types | Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Krishnamurthy Dhakshinamurthy, Arun Thandapani | 2018-09-11 |
| 10055267 | Block management scheme to handle cluster failures in non-volatile memory | Dinesh Kumar Agarwal, Ramkumar Ramamurthy | 2018-08-21 |
| 9971514 | Dynamic logical groups for mapping flash memory | Vivek Shivhare, Abhijeet Manohar | 2018-05-15 |
| 9875039 | Method and apparatus for wear-leveling non-volatile memory | Chetan Agrawal, Dinesh Kumar Agarwal | 2018-01-23 |