Issued Patents 2018
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10163490 | P-type field-effect transistor (PFET)-based sense amplifiers for reading PFET pass-gate memory bit cells, and related memory systems and methods | Hoan Huu Nguyen, Francois Ibrahim Atallah, David Joseph Winston Hansquine, Jihoon Jeong | 2018-12-25 |
| 10115481 | Read-assist circuits for memory bit cells employing a P-type field-effect transistor (PFET) read port(s), and related memory systems and methods | Francois Ibrahim Atallah, David Joseph Winston Hansquine, Jihoon Jeong, Hoan Huu Nguyen | 2018-10-30 |
| 10024916 | Sequential circuit with error detection | James W. Tschanz, Nam Sung Kim, Janice C. Lee, Christopher B. Wilkerson, Shih-Lien Linus Lu +2 more | 2018-07-17 |
| 10026456 | Bitline positive boost write-assist circuits for memory bit cells employing a P-type Field-Effect transistor (PFET) write port(s), and related systems and methods | Jihoon Jeong, Francois Ibrahim Atallah, David Joseph Winston Hansquine, Hoan Huu Nguyen | 2018-07-17 |
| 10009016 | Dynamically adaptive voltage-frequency guardband control circuit | Lam Ho, Navid Toosizadeh, Shih-Hsin Jason Hu, Mohammad Reza Kakoee, Saravana Krishnan Kannan | 2018-06-26 |
| 9984730 | Negative supply rail positive boost write-assist circuits for memory bit cells employing a P-type field-effect transistor (PFET) write port(s), and related systems and methods | Jihoon Jeong, Francois Ibrahim Atallah, David Joseph Winston Hansquine, Hoan Huu Nguyen | 2018-05-29 |
| 9947406 | Dynamic tag compare circuits employing P-type field-effect transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and related systems and methods | Francois Ibrahim Atallah, David Joseph Winston Hansquine, Jihoon Jeong, Hoan Huu Nguyen | 2018-04-17 |
| 9940992 | Leakage-aware activation control of a delayed keeper circuit for a dynamic read operation in a memory bit cell | Francois Ibrahim Atallah, Hoan Huu Nguyen | 2018-04-10 |
| 9915968 | Systems and methods for adaptive clock design | Palkesh Jain, Virendra Bansal, Manoj Mehrotra | 2018-03-13 |