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Multi-level system memory with near memory scrubbing based on predicted far memory idle time |
Zhe Wang, Zeshan A. Chishti |
2018-11-06 |
| 10108549 |
Method and apparatus for pre-fetching data in a system having a multi-level system memory |
Zhe Wang, Zeshan A. Chishti, Seth H. Pugsley, Alaa R. Alameldeen, Shih-Lien Linus Lu |
2018-10-23 |
| 10102134 |
Instruction and logic for run-time evaluation of multiple prefetchers |
Zeshan A. Chishti, Seth H. Pugsley, Peng-Fei Chuang, Robert L. Scott, Aamer Jaleel +2 more |
2018-10-16 |
| 10024916 |
Sequential circuit with error detection |
Keith Alan Bowman, James W. Tschanz, Nam Sung Kim, Janice C. Lee, Shih-Lien Linus Lu +2 more |
2018-07-17 |
| 10019360 |
Hardware predictor using a cache line demotion instruction to reduce performance inversion in core-to-core data transfers |
Ren Wang, Andrew J. Herdrich |
2018-07-10 |
| 10007620 |
System and method for cache replacement using conservative set dueling |
Seth H. Pugsley, Roger Gramunt, Jonathan C. Hall, Prabhat Jain |
2018-06-26 |
| 9921961 |
Multi-level memory management |
Alaa R. Alameldeen, Zhe Wang, Zeshan A. Chishti |
2018-03-20 |
| 9921972 |
Method and apparatus for implementing a heterogeneous memory subsystem |
Alaa R. Alameldeen, Zeshan A. Chishti, Jaewoong Sim |
2018-03-20 |