HI

Hirotaka Ichikawa

Toshiba Memory: 2 patents #200 of 956Top 25%
Overall (2018): #144,769 of 503,207Top 30%
2
Patents 2018

Issued Patents 2018

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
9977855 Method of wiring layout, semiconductor device, program for supporting design of wiring layout, and method for manufacturing semiconductor device Chikaaki Kodama, Koichi Nakayama, Toshiya Kotani, Shigeki Nojima, Fumiharu Nakajima 2018-05-22
9953126 Method of wiring layout, semiconductor device, program for supporting design of wiring layout, and method for manufacturing semiconductor device Chikaaki Kodama, Koichi Nakayama, Toshiya Kotani, Shigeki Nojima, Fumiharu Nakajima 2018-04-24