Issued Patents 2018
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10162918 | Integrated circuit retiming with selective modeling of flip-flop secondary signals | Mahesh A. Iyer, Robert Walker | 2018-12-25 |
| 10157247 | Method and apparatus for performing rewind structural verification of retimed circuits driven by a plurality of clocks | Mahesh A. Iyer | 2018-12-18 |