Issued Patents 2018
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10032524 | Techniques for determining local interconnect defects | Sagar Magia, Jayavel Pachamuthu | 2018-07-24 |
| 9953717 | NAND structure with tier select gate transistors | Jayavel Pachamuthu, Peter Rabkin | 2018-04-24 |
| 9934872 | Erase stress and delta erase loop count methods for various fail modes in non-volatile memory | Sagar Magia, Jayavel Pachamuthu | 2018-04-03 |
| 9881929 | Multi-tier memory stack structure containing non-overlapping support pillar structures and method of making thereof | Pradhyumna Ravikirthi, Jayavel Pachamuthu, Peter Rabkin | 2018-01-30 |