Issued Patents 2018
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10162756 | Memory-efficient last level cache architecture | Jayesh Gaur, Ayan Mandal, Anant Vithal Nori | 2018-12-25 |
| 10013352 | Partner-aware virtual microsectoring for sectored cache architectures | Jayesh Gaur, Mukesh Agrawal, Mainak Chaudhuri | 2018-07-03 |
| 9921839 | Coordinated thread criticality-aware memory scheduling | Lavanya Subramanian, Nithiyanandan Bashyam, Anant Vithal Nori | 2018-03-20 |