Issued Patents 2018
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10162756 | Memory-efficient last level cache architecture | Jayesh Gaur, Ayan Mandal, Sreenivas Subramoney | 2018-12-25 |
| 9921839 | Coordinated thread criticality-aware memory scheduling | Lavanya Subramanian, Sreenivas Subramoney, Nithiyanandan Bashyam | 2018-03-20 |