Issued Patents 2018
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10164099 | Device with diffusion blocking layer in source/drain region | Pei Zhao, Baofu Zhu, Francis Benistant | 2018-12-25 |
| 10084093 | Low resistance conductive contacts | Shiv Kumar Mishra, Sunil Kumar Singh | 2018-09-25 |
| 10083904 | Metholodogy for profile control and capacitance reduction | Sunil Kumar Singh | 2018-09-25 |
| 10079308 | Vertical transistor structure with looped channel | Hui Zang, Josef S. Watts | 2018-09-18 |
| 10062689 | Method to fabricate vertical fin field-effect-transistors | — | 2018-08-28 |
| 10056486 | Methods for fin thinning providing improved SCE and S/D EPI growth | Pei Zhao, Zhenyu Hu | 2018-08-21 |
| 10002797 | Chip integration including vertical field-effect transistors and bipolar junction transistors | — | 2018-06-19 |
| 10002793 | Sub-fin doping method | Jiehui Shu, David Paul Brunco, Jinping Liu, Baofu Zhu | 2018-06-19 |
| 9966433 | Multiple-step epitaxial growth S/D regions for NMOS FinFET | Zhiqing Li, Francis Benistant | 2018-05-08 |
| 9966313 | FinFET device and method of manufacturing | Baofu Zhu, Srikanth B. Samavedam | 2018-05-08 |
| 9960113 | Method to fabricate a high performance capacitor in a back end of line (BEOL) | Sunil Kumar Singh | 2018-05-01 |
| 9947788 | Device with diffusion blocking layer in source/drain region | Pei Zhao, Baofu Zhu, Francis Benistant | 2018-04-17 |
| 9923046 | Semiconductor device resistor structure | Hui Zang, Josef S. Watts | 2018-03-20 |