Issued Patents 2018
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10163635 | Asymmetric spacer for preventing epitaxial merge between adjacent devices of a semiconductor and related method | Yi Qi, Hui Zang, Hsien-Ching Lo, Judson R. Holt | 2018-12-25 |
| 10163915 | Vertical SRAM structure | Hui Zang | 2018-12-25 |
| 10164006 | LDMOS FinFET structures with trench isolation in the drain extension | Jagar Singh, Hui Zang | 2018-12-25 |
| 10134739 | Memory array with buried bitlines below vertical field effect transistors of memory cells and a method of forming the memory array | Hui Zang, Rinus Tek Po Lee | 2018-11-20 |
| 10121893 | Integrated circuit structure without gate contact and method of forming same | Hui Zang, Manfred Eller, Min-hwa Chi | 2018-11-06 |
| 10121878 | LDMOS finFET structures with multiple gate structures | Jagar Singh, Hui Zang | 2018-11-06 |
| 10068902 | Integrated circuit structure incorporating non-planar field effect transistors with different channel region heights and method | Yanping Shen, Hui Zang, Hsien-Ching Lo, Yongjun Shi, Randy W. Mann +4 more | 2018-09-04 |
| 10026740 | DRAM structure with a single diffusion break | Hui Zang, Josef S. Watts | 2018-07-17 |
| 9876010 | Resistor disposed directly upon a sac cap of a gate structure of a semiconductor structure | Hui Zang, Jagar Singh | 2018-01-23 |