ZQ

Zhehong Qian

CS Cadence Design Systems: 3 patents #4 of 223Top 2%
Overall (2018): #49,913 of 503,207Top 10%
3
Patents 2018

Issued Patents 2018

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
10162522 Architecture of single channel memory controller to support high bandwidth memory of pseudo channel mode or legacy mode Xiaofei Li, Yanjuan Zhan, Ying Li, Buying Du 2018-12-25
10067689 Method and apparatus for high bandwidth memory read and write data path training Guangxi Ying, Xiaobo ZHANG, Yanjuan Zhan 2018-09-04
9881664 Per-group delay line architecture to de-skew input/output timing between a high bandwidth memory (HBM) physical (PHY) interface and the HBM device Guangxi Ying, Yanjuan Zhan, Ying Li 2018-01-30