YL

Ying Li

CS Cadence Design Systems: 2 patents #20 of 223Top 9%
📍 Shanghai, CA: #133 of 377 inventorsTop 40%
Overall (2018): #88,311 of 503,207Top 20%
2
Patents 2018

Issued Patents 2018

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
10162522 Architecture of single channel memory controller to support high bandwidth memory of pseudo channel mode or legacy mode Xiaofei Li, Zhehong Qian, Yanjuan Zhan, Buying Du 2018-12-25
9881664 Per-group delay line architecture to de-skew input/output timing between a high bandwidth memory (HBM) physical (PHY) interface and the HBM device Guangxi Ying, Yanjuan Zhan, Zhehong Qian 2018-01-30