PA

Puneet Arora

CS Cadence Design Systems: 3 patents #4 of 223Top 2%
HP HP: 1 patents #353 of 955Top 40%
📍 Atrauli, TX: #2 of 2 inventorsTop 100%
Overall (2018): #37,733 of 503,207Top 8%
4
Patents 2018

Issued Patents 2018

Showing 1–4 of 4 patents

Patent #TitleCo-InventorsDate
10095822 Memory built-in self-test logic in an integrated circuit design Navneet Kaushik, Steven Lee Gregor, Norman Robert Card 2018-10-09
10007489 Automated method identifying physical memories within a core or macro integrated circuit design Steven Lee Gregor, Norman Robert Card 2018-06-26
9898235 Marking agent credit adjustments Shinoj Bhaskaran, Ruby Tomar, Diane R. Hammerstad 2018-02-20
9865362 Method and apparatus for testing error correction code (ECC) logic and physical memory onboard a manufactured integrated circuit (IC) Steven Lee Gregor, Norman Robert Card, Navneet Kaushik 2018-01-09